Many devices rely on the synchronization of an internal signal frequency to an external signal frequency. This synchronization may be used for frequency tuning in communications devices (e.g., phones, GPS devices, etc.), or clock synchronization in a variety of devices such as measurement devices. This synchronization is often effected by phase-lock techniques.
One type of measurement device is a combination signal analyzer/network analyzer (SANA). The SANA instrument typically contains a single reference frequency oscillator to which other oscillators in the system are phase-locked. These oscillators are used for frequency translation in the receiver conversion chain as well as for sampling clocks in the data acquisition system. As will be appreciated the frequency accuracy and stability of these oscillators affect the quality of measurements.
Often, it is useful to phase-lock the internal oscillators to an external signal to eliminate relative frequency or timing errors, or both, between the measuring instrument and the equipment under test. In addition absolute frequency accuracy of spectrum measurements and network S-parameter measurements are also greatly improved by using comparatively high accuracy reference sources such as those derived from atomic clocks.
The internal oscillator (also referred to as the internal reference source) is used to derive the local oscillators and clocks used in the system. To improve the instrument frequency accuracy, a continuous-time phase-lock loop (CTPLL) is often used to lock the internal reference source (fo) to an external reference source (fref). A CTPLL can be considered a frequency multiplier where the output frequency fo is an integer-multiple R of the reference frequency, fref. For a given design, fo is fixed by system design considerations and in many designs R is a fixed integer. Because R is an integer the loop can only lock to a limited set of reference frequencies defined by the equation fo/R.
Limiting the CTPLL multiplication to a fixed integer R is highly desirable in mobile instruments to simplify the required circuitry. However, this presents a serious limitation because it eliminates the possibility of frequency diversity as well as restricting the single fref to an integer sub-multiple of fo. These constraints can be partially relaxed by allowing R to be variable but this still constrains fref to steps of fo/R(R−1). A further refinement of the CTPLL is the addition of a fractional divider for R in the feedback. However, while this provides the desired frequency diversity and arbitrary ratio of fo/fref, the required circuit complexity is significantly increased and often requires mixed signal technologies with correspondingly higher power consumption and board space requirements. As will be appreciated, this added complexity is undesirable both from a space perspective and from a cost perspective.
There is a need, therefore, for a phase-locking that overcomes at least the shortcoming of known phase-lock techniques described above.